Logic blocks of a circuit design are sometimes replicated in order to make certain improvements in the implemented design. For example, fanout-free regions of a logic cone may be created in order to apply combinatorial synthesis optimizations. In another example, a flip-flop may be replicated in order to reduce the number of outputs for a high-fanout signal. The replication of logic occurs in the logic synthesis stage.
With each replication, the fanout on the output side of the logic is reduced at the expense of an increased number of pins on the input side of the replicated logic. The replicate logic blocks may have a negative impact on circuit performance, because not all replicate logic blocks may be necessary and extra unnecessary blocks occupy circuit area and consume extra power.
Logic replication may create additional problems in designs targeted to programmable integrated circuits such as field programmable gate arrays (FPGAs). For example, in some FPGAs from XILINX®, Inc., each flip-flop in a slice needs to be driven by the same clock and control signals (the “control set”). Flip-flop replications may result in fitting problems due to the control set requirements.
The present invention may address one or more of the above issues.